1. Field of the Invention
The present invention relates to inductors within devices of semiconductor chips, and more particularly, to the formation of inductors within a semiconductor device.
2. Description of the Related Art
Today""s semiconductor devices are continually being pushed to meet stricter demands. As devices using this technology inundate the marketplace, consumers place higher demands on them. These demands include smaller, more compact devices with greater functionality. The growing market of wireless communications requires that smaller integrated circuits have greater functionality.
In order to meet these demands, RF integrated circuits must be more efficient in addition to being decreased in size along with the decreased size of components contained on the circuits. Due to the interest in RF circuitry, there is a greater push to design inductors as a passive element within a semiconductor device. An inductor is typically constructed in a semiconductor substrate using metallization lines formed in the shape of a spiral. The spiral shape of the inductor allows the structure to produce an inductance. Prior art inductors typically used aluminum (Al) for the metallization layers which form the spirals of the inductor.
One measure of efficiency of an inductor is its quality factor. The higher the quality factor, the greater the efficiency of the inductor. Thus, an inductor having a high quality factor is preferred. The quality factor of an integrated circuit is limited by parasitic losses within the substrate itself. These losses include high resistance through metal layers of the inductor itself. Consequently, in order to achieve a high quality factor, resistance within the inductor should be held to a minimum. One technique used to minimize the resistance within the inductor is increasing the thickness of metal used to fabricate the inductor. In order to accomplish this, prior art inductors are placed at the top level of the semiconductor substrate where metallization layers are thicker and where further planarization is not as critical. The inductor is also placed as far from the substrate as possible to reduce capacitance to substrate interactions with the substrate. Nevertheless, this configuration does not allow a high quality factor nor does it optimize the ability to reduce resistance.
As mentioned earlier, aluminum metallization layers were used to form spirals of prior art inductors. The use of aluminum minimized the ability to increase the thickness of the metal used to form the inductor, thereby increasing the resistance of an inductor. For example, individual aluminum layers were separated by layers of dielectric formed in the semiconductor wafer. In order to increase the thickness of metal used in an inductor, tungsten (W) interconnects were used in the layers of dielectric separating the aluminum layers. However, the use of tungsten to form an inductor is undesirable since tungsten has a high resistance which decreases the quality factor and the overall efficiency of an inductor using tungsten. In addition, tungsten interconnects generally had small via holes that do not greatly increase the thickness of metal used in an inductor having tungsten.
In view of the foregoing, there is a need for a method of making inductors in standard interconnect metallization structures. There is also a need for inductor structures that have a high quality factor. Additionally, there is a need for an inductor which can be fabricated without additional fabrication operations.
Broadly speaking, the present invention fills these needs by providing an inductor having a high quality factor and low resistance. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for making a semiconductor inductor is disclosed. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench and a first inductor trench within the oxide layer. The first inductor trench is etched to define an inductor geometry. Next, at least one via is etched in the interconnect metallization trench and a second inductor trench is etched over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry of the first inductor trench. The at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with a conductive material after the at least one via and the second inductor trench are etched in the oxide layer.
In another embodiment, a method for making a multi-level semiconductor inductor is disclosed. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench and a first inductor trench within the oxide layer. The first inductor trench is etched such that an inductor geometry is defined within the oxide layer. The oxide layer is etched again to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench is etched such that it also has the inductor geometry. After the at least one via and the second inductor trench are formed in the oxide layer, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with a copper material. The filled at least one via, second inductor trench, interconnect metallization trench and first inductor trench define a first inductive metallization structure.
The etch operations are performed on a next oxide layer disposed over the first inductive metallization structure to form another at least one via, another second inductor trench, another interconnect metallization trench and another first inductor trench. After the etch operation is completed, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with a copper material to define a second inductive metallization structure. The first and second metallization structures provide the multi-level semiconductor inductor with a reduced resistance and an increased quality factor.
In a further embodiment, a method for making a semiconductor inductor is disclosed. An inductor trench and a metallization trench are formed in an oxide layer such that the inductor trench defines an inductor geometry. A via trench and an additional inductor trench are then formed in the oxide layer such that the additional inductor trench also defines the inductor geometry. The via trench, the additional inductor trench, the inductor trench and the metallization trench are then filled with a metal whereby the filled additional inductor trench and the filled inductor trench define the semiconductor inductor, the filled metallization trench defines a metallization line and the filled via trench defines a conductive via.
In yet another embodiment of the present invention, an inductor structure is disclosed. The inductor structure includes a first oxide layer having a first thickness and a first metallization level disposed in a first part of the first oxide layer with the first metallization level having an inductor geometry. A second metallization level having the inductor geometry is disposed over the first metallization level in a second part of the first oxide layer. The first part of the first oxide layer and the second part of the first oxide layer define the first thickness of the first oxide layer. The inductor structure of the first metallization level and the second metallization level define a multi-level inductor structure having a low resistance characteristic and a high quality factor.
In another embodiment of the present invention, a semiconductor inductor is disclosed. The semiconductor inductor includes a first inductor structure which is of a copper material. The first inductor has an inductor geometry and the first inductor is defined to a partial depth within an oxide layer that is disposed over a substrate. A metallization line which is of the copper material is defined in the oxide layer to the same partial depth of the oxide layer. The semiconductor inductor also includes a conductive via of the same copper material defined in a remaining depth of the oxide layer relative to the partial depth such that the conductive via interconnects the metallization line to another feature. In addition, a second inductor structure of the same copper material and having the inductor geometry forms the semiconductor inductor. The second inductor structure is disposed in the remaining depth of the oxide layer.
The many advantages of the current invention should be recognized. The present invention allows for the formation of a semiconductor inductor using standard fabrication techniques which do not require additional fabrication steps. In addition, the inductor of the present invention can be fabricated to have low resistance and a high quality factor. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.